Address transition detection ATD circuits are employed in memory devices to detect a change in the user-supply address bits, forming an address transition to access a new location in memory. As the address transition is detected by the memory device, a new address has been supplied by the user, and this address must be decoded by the decoding circuitry of the memory device in order to access the actual memory address. When a memory address is to be accessed, the data path to and from the memory address must be precharged in preparation for the transfer of this data. This precharging may involve precharging a capacitor of a row and column to be addressed. Typically, a pulse from the ATD circuit is used in the memory to begin precharging this path.
FIG. 1 illustrates ATD circuit 100. The ATD circuit 100 includes a delay circuit 102 and an exclusive OR, XOR, 104. The circuit 104 produces a high output or logical "1" whenever the inputs to the XOR circuit 104 are different. The XOR circuit 104 produces a low output or logical zero output whenever the inputs to the XOR circuit are the same.
FIG. 2 illustrates that the input is normally unchanging high logical 1 or low/logical 0 while no address transition is requested. If the address transition is requested, the input changes. The output from circuit 104 is low while both the input and the output of circuit 102 changes from high to low or low to high. When the input is not equal, the output of circuit 102, and the output to circuit 104 is high. The output from circuit 104, is illustrated in FIG. 2. Initially, the output of circuit 104 is low while both the input and output from delay circuit 102 is high. When input is low due to an address transition, the output of delay circuit 102 remains high. The output of circuit 104 is high in response to the unequal input to circuit 104. Afar a predetermined period of time, the output of circuit 102 goes low. In response, the output of circuit 104 goes low. In addition, FIG. 2 illustrates a second address transaction. However, as illustrated in FIG. 2, the width of the output pulse of circuit 104 is dependent upon the time delay generated by circuit 102.
As illustrated in FIG. 3, a narrow input pulse results in a narrow output pulse from circuit 104. This narrow width pulse from the output of circuit 104 is insufficient to precharge the path.